† Corresponding author. E-mail:
‡ Corresponding author. E-mail:
Project supported by the National Natural Science Foundation of China (Grant Nos. 61176100 and 61274112), the University Development Fund of the University of Hong Kong, China (Grant No. 00600009), and the Hong Kong Polytechnic University, China (Grant No. 1-ZVB1).
An equivalent distributed capacitance model is established by considering only the gate oxide-trap capacitance to explain the frequency dispersion in the C–V curve of MOS capacitors measured for a frequency range from 1 kHz to 1 MHz. The proposed model is based on the Fermi–Dirac statistics and the charging/discharging effects of the oxide traps induced by a small ac signal. The validity of the proposed model is confirmed by the good agreement between the simulated results and experimental data. Simulations indicate that the capacitance dispersion of an MOS capacitor under accumulation and near flatband is mainly caused by traps adjacent to the oxide/semiconductor interface, with negligible effects from the traps far from the interface, and the relevant distance from the interface at which the traps can still contribute to the gate capacitance is also discussed. In addition, by excluding the negligible effect of oxide-trap conductance, the model avoids the use of imaginary numbers and complex calculations, and thus is simple and intuitive.
Recently, III–V compound semiconductors, especially InGaAs, have been recognized as one of the leading candidates to replace silicon for digital CMOS applications, because of their higher carrier mobility.[1–3] However, as the MOSFET dimensions are continually scaled down, high-k materials, e.g., Al2O3,[4] HfO2,[5] La2O3,[6] and ZrO2,[7] are employed to replace SiO2 as a gate dielectric because their larger k values allow for the use of a thicker gate dielectric for suppressing the gate leakage current. However, the high-k gate dielectrics often have more traps, which result in serious frequency dispersion of the capacitance–voltage (C–V) curve, especially in the accumulation region.[8–12] The conventional interface-state theory cannot explain this phenomenon because the time constant of the interface states is too small for typical measurement frequencies (1 kHz to 1 MHz) to make the interface states respond to the applied voltage.[13,14] Therefore, many relevant models have focused on the traps in the gate oxide, which have large time constant, and thus can interact with the electrons in the conduction band of the semiconductor via a tunneling mechanism.[15–19] These frequency-dispersion models based on oxide traps include the lumped RC circuit model,[16,17] the distributive-transconductance model,[18] and the distributed circuit model,[19] which involves both the capacitance and conductance effects of the oxide traps. It is believed that the traps in the gate dielectric can capture and emit charges to produce capacitance and conductance. Although it has been pointed out that errors probably exist in the distributive-transconductance model,[20] it could still prove that the oxide traps can result in frequency dispersion in the C–V and G–V curves. In addition, some researchers regarded the traps in the oxide as near-interface traps,[21,22] and the relevant models were established based on the traditional interface-state theory and by considering only the capacitance effect of the near-interface states and interface states. These models could well be used to simulate the dispersion effect in the depletion region of the C–V curve for 1 kHz to 1 MHz, and extract the interface-state and near-interface-state densities by measuring the gate capacitance at different temperatures, but the dispersion effect in the accumulation region cannot be successfully accounted for. Therefore, in this work, an equivalent distributed capacitance model considering only the capacitance effect of the oxide traps in the MOS devices, e.g., Al2O3/InGaAs MOS devices, is developed to explain the frequency dispersion of C–V curve, especially in the accumulation region, for the frequency range from 1 kHz to 1 MHz. The proposed model is made simple and intuitive by excluding the conductance effect of the oxide traps. This approximation is confirmed to be reasonable by the good agreement between simulated results and experimental data, demonstrating that the oxide traps are the major origin to cause the frequency dispersion in the C–V curve.
Under equilibrium, the probability that an oxide trap in an MOS device is occupied by an electron obeys the Fermi–Dirac statistics[20]
When a small ac signal of δVg = V eiωt is applied to the gate electrode, the trap-level occupation probability becomes[21]
![](cpb_25_11_118502/cpb160596ieqn1.gif)
![](cpb_25_11_118502/cpb160596ieqn2.gif)
Thus, the Qbt variation induced by δVg can be expressed as
Since the term f0 (1 − f0) is sharply peaked at E = Ef, κ is set to be a constant when E = Ef in the integration.[23] So integrating Eq. (
For a given gate dc bias, the oxide traps with distance x and energy Et can change occupancy in response to a small ac signal modulation,[24] with the highest occupation probability when Et = Ef by exchanging charge with the conduction band of the semiconductor via tunneling.[24] So it is reasonably suggested that the small-signal capacitance is produced mainly by those traps at Et = Ef (κ is a constant in the integration).
The proposed model is an equivalent distributed capacitance model, as shown in Fig.
As shown in Fig.
Subtracting C(x) and dividing by Δx on both sides of Eq. (
In the following simulations, InGaAs MOS devices are considered and simulated results are shown in Figs.
![]() | Fig. 3. Comparison between simulated results (solid line) and experimental data (open circles) for a Pd/4.5-nm Al2O3/p-InGaAs MOS device with the gate biased at −1.8 V. |
![]() | Fig. 4. Comparison between simulated results (solid line) and experimental data (open circles) for a 7-nm Al2O3/n-InGaAs MOS device biased in the accumulation region. |
![]() | Table 1. The parameters used in simulation for different gate biases corresponding to Figs. |
The experimental data in Fig.
The experimental data in Fig.
As can be seen from Figs.
Figure
![]() | Fig. 5. Comparison between the proposed model (Eq. ( |
It is worth pointing out that the effect of the parasitic resistance in series with the MOS capacitor is not considered in the model because it plays no role when the measurement frequency is only a few kilohertz.[24] However, dispersion is still observed in the measurement, indicating that the dispersion is indeed mainly from the capacitance effect of the oxide traps rather than the parasitic resistance.
Also, the capacitance from the interface states (Cit) can be expressed as
As expressed in Eq. (
Figure
Figure
![]() | Fig. 7. Relation between the trap distance from the interface and the interface-state time constant τ0 with ωτ (x) = 1. |
An equivalent distributed capacitance model considering only the oxide-trap capacitance is built to explain the frequency dispersion in the measured capacitance of Al2O3/InGaAs MOS capacitors, especially in accumulation and near flatband. The model is based on the Fermi–Dirac statistics and the charging/discharging effects of the oxide traps induced by a small ac signal, and differs from other models based on the interface-state theory. The simulated results are in good agreement with experimental data, confirming the validity of the proposed model. The model can explain the frequency-dispersion phenomenon in the C–V curve of both n- and p-type devices under different gate biases. In addition, it is fundamentally different from the conventional interface-state models in which the time constant is too small for the oxide traps to respond to ac signals with frequency from 1 kHz to 1 MHz. Moreover, the proposed model is simple and intuitive (owing to its limited consideration of only trap capacitance), and is sufficiently accurate, implying that the conductance effect of the oxide traps has a smaller contribution to the frequency dispersion of the C–V curve. The simulated results indicate that only those traps adjacent to the oxide/semiconductor interface can enhance the capacitance dispersion of MOS capacitor under accumulation and near flatband, while the effects of the traps far from the interface are negligible.
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